Memory bandwidth has become a bottleneck to system performance in high-performance computing, high-end servers, graphics, and (very soon) mid-level servers. Microprocessor enablers are doubling cores and threads-per-core to greatly increase performance and workload capabilities by distributing work sets into smaller blocks and distributing them among an increasing number of work elements, i.e. cores. Having multiple computer elements per processor results in an increasing amount of memory per computer element. This results in a greater need for memory bandwidth and memory density to be tightly coupled to a processor to address these challenges. Current memory technology roadmaps do not provide the performance to meet the central processing unit (CPU) and graphics processing unit (GPU) memory bandwidth goals.
To address the need for memory bandwidth and memory density to be tightly coupled to a processor, a hybrid memory cube (HMC) may be implemented so that memory may be placed on the same substrate as a controller enabling the memory system to perform its intended task more optimally. The HMC may feature a stack of individual memory die connected by internal vertical conductors, such as through-silicon vias (TSVs), which are vertical conductors that electrically connect a stack of individual memory die with a controller, such as to combine high-performance logic with dynamic random-access memory (DRAM). HMC delivers bandwidth and efficiencies while less energy is used to transfer data and provides a small form factor. In one embodiment of a HMC, the controller comprises a high-speed logic layer that interfaces with vertical stacks of DRAM that are connected using TSVs. The DRAM handles data, while the logic layer handles DRAM control within the HMC.
In other embodiments, a HMC may be implemented on, for example, a multi-chip module (MCM) substrate or on a silicon interposer. A MCM is a specialized electronic package where multiple integrated circuits (ICs), semiconductor dies or other discrete components are packaged onto a unifying substrate thereby facilitating their use as a component (e.g., thus appearing as one larger IC). A silicon interposer is an electrical interface routing between one connection (e.g., a socket) and another. The purpose of an interposer is to spread a connection to a wider pitch or to reroute a connection to a different connection.
However, the DRAM stack in a HMC has more bandwidth and signal count than many applications can use. The high signal count and high bandwidth of the DRAM stack in a HMC makes a cost effective host interface difficult.